The present invention relates to digital image processing systems and methods for efficiently buffering pixel values relating to digital images. Digital image processing typically follows a rasterized path. Pixel values are read and processed from left to right within a single line, and lines are processed from top to bottom. Many image processing operations such as filtering and scaling operate on areas that span multiple lines and columns of a digital image. For these types of operations, line buffering is necessary to temporarily store pixel values for multiple lines. Even though an area based algorithm may only use a small number of pixels within a given line, the entire line must be buffered when data from subsequent lines are also required.
When an image processing operation is implemented in hardware, the resolution and image width will define the amount of memory, typically SRAM, needed for buffering. If the line resolution doubles, the amount of memory doubles. Typically the amount of SRAM available for buffering is fixed within an Application Specific Integrated Circuit (ASIC) implementing the desired function. Thus, a decision regarding the size of the buffer must be made early on in a design project in which line buffering will be required. If a later product needs more buffering, or if specifications change, the ASIC must be re-designed. This can add significant cost and delay to the project.